1. Field of the Invention
The present invention relates in general to electronic packages and methods of forming thereof, and in particular pertains to an electronic package which has a thermally conductive member encapsulated with the semiconductor chip; and which is adapted for chip-scale or near-chip-scale applications of both wire-bond and flip-chip packages.
In essence, a particular type of electronic package which consists of a PBGA (plastic ball grid array) package, and which is applicable to chip-scale or near-chip-scale applications, and is essentially constituted of a chip mounted on an organic, wire carrier or circuitized substrate the size of which may extend beyond the peripheral dimensions of the semiconductor chip. The foregoing relates to both wire-bond and flip chip packages and wherein in order to protect the semiconductor chip from the deleterious or debilitating effects of the environment, it is generally desirable to form an insulating body about the chip, this body generally being in the form of a molded epoxy material forming an encapsulant. Generally, as is well known in the technology, interfacial stresses which are generated between the encapsulating molded material, such as the epoxy which may be a thermoset plastic resin, and the circuitized substrate or chip carrier, can be quite considerable in magnitude and may result in delamination of the components as a result of exposure to moisture or during thermal cycling. This will adversely affect the reliability and possibly even completely destroy the electrical interconnections of the electronic package and the functional integrity thereof, leading to potentially extensive financial and economic losses. Heretofore, when applying the molded material producing the protective structure encompassing the semiconductor chip and forming the physical bond with the carrier or circuitized substrate on which the chip is positioned, the molded material has been confined to engagement with the surface on the side of the carrier or substrate on which the semiconductor chip is mounted, whereby the opposite or distal side of the carrier, on which there is normally disposed an array of solder balls (BGA""s) is left unencapsulated so as to provide electrical connecting access for the solder balls. Although the encapsulation of the semiconductor chip and the resulting bonding with the circuitized substrate or carrier is effected by a molded compound generally constituted of an epoxy, the tendency in industry, at this time has been a shifting towards the use of mold compounds or bodies forming the encapsulate for the electronic package which has a lower coefficient of thermal expansion (CTE) than heretofore, whereby the interfacial stresses which extend normal to the surface of the carrier or circuitized substrate facing towards the semiconductor chip are reduced in the region extending about the periphery of the semiconductor chip. This, in essence, increases the bending of the electronic semiconductor chip-mounting package and decreases the fatigue life expectancy of the ball grid arrays (BGA). Although the stresses which are generated as a result of bending are ordinarily not a problem to the degree in chip-scale packages as they would be in larger PBGA""s, these stresses must be still minimized due to the effect on BGA fatigue and to enable an increase in their length of service life. The fatigue life of such BGA""s represents a particular problem for chip-scale packages, inasmuch as the solder ball size and the pitch between balls must be decreased in order to be able to provide sufficient numbers of interconnections with the small package size, whereby both of these decreases in pitch and size result in a shorter fatigue life for the structure.
Although the prior art has addressed itself to this problem by providing various improved bonding interconnections between the mold compound or material encapsulating a semiconductor chip and by also concurrently encapsulating the surface and, as required, potentially the peripheral side surfaces of the carrier or circuitized substrate, problems are still encountered in providing an adequate degree of adhesion between the components which will prevent delamination under conditions of bending or thermal cycling This problem has been addressed to some extent in co-pending U.S. patent application Ser. No. 09/430,075, (Attorneys Docket EN998109), in which there are disclosed various embodiments directed to the encapsulation of semiconductor chips or electronic packages with a mold material, such as a thermoset plastic or molded epoxy resin, and wherein the encapsultaing material also encompasses the periphery of the chip-mounting substrate or circuitized carrier and the surface thereof which faces towards the mounted semiconductor chip.
2. Discussion of the Prior Art
A number of publications are disclosed in the technology which concern themselves with the use of an encapsulating material extending about and bonding semiconductor chips to diverse kinds of circuitized substrates or carriers.
Thus, Hiruta U.S. Pat. No. 5,998,861 discloses a semiconductor device with a ball grid array (BGA) wherein an epoxy material provides an encapsulant between a semiconductor chip and the facing surface of a carrier for the ball grid array.
Odashima, et al. U.S. Pat. No. 5,998,243 discloses a method for the manufacturing of semiconductor devices and an apparatus, whereby a resin material forms an encapsulate between a semiconductor chip and a carrier on which the chip is mounted.
Yamada, et al. U.S. Pat. No. 5,864,178 discloses a semiconductor device with an encapsulating material constituting of a curable resin for bonding a flip-chip bonded semiconductor chip to the facing surface structure of a substrate or circuitized carrier body mounting the chip.
Other publications which concern themselves to some extent with various encapsulating materials adapted to be employed in electronic packages are Wang et al., U.S. Pat. No. 5,817,545; Thompson et al., U.S. Pat. No. 5,218,234, and Banerji et al., U.S. Pat. No. 5,203,076.
Although the foregoing publications each deal in different measures or degrees with various aspects in providing apparatus and methods for encapsulating semiconductor chips in order to protect the components of the electronic package against potentially deleterious environmental influences, and by utilizing various suitable encapsulating resins or thermosetting plastic materials, such as molded epoxy compounds or silicones, all of these publications limit the encapsulating interconnections or bonding between the circuitized semiconductor chip and the carrier or substrate in that the adhesion or bonding is only effected between the semiconductor chip and the surface of the substrate facing towards the superimposed semiconductor chip, and, at times as required, extending about the peripheral sides or edges of the substrate.
Accordingly, in order to significantly improve upon the foregoing methods and structure for adhesively bonding the semiconductor chip to a circuitized carrier or substrate on which the chip is positioned, and to concurrently form an encapsulating structure protecting the semiconductor chip, the present invention provides for a mold compound, such as a thermosetting plastic resin or epoxy to not only extend between the surface of the circuitized substrate or carrier facing the semiconductor chip, and possibly about the peripheral sides of the carrier, but to also at least extend over and encompass the peripheral edge portions of the opposite surface of the carrier or circuitized substrate distal to or facing away from the chip, which will counteract any tendency towards delamination between the components of the electronic package, in effect, between the semiconductor chip and the circuitized substrate or carrier; and considerably reduce stresses and strains so as to preserve the reliability of the electronic package.
In particular, in the utilization of transfer molding when encapsulating a semiconductor chip in an electronic package, such as a PBGA package, heretofore the mold material has been confined to the side of the carrier or substrate on which the chip is mounted, with the opposite or distal side of the carrier on which there is disposed an array of solder balls (BGA) being left exposed and unencapsulated.
In contrast with the foregoing, pursuant to the present invention, the encapsulant, such as a thermoset plastic or molded epoxy, is extended about the peripheral sides of the substrate or circuitized carrier so as to contact and sealingly cover at least the lower edge surface portions of the carrier, preferably a portion of the surface mounting the BGA and perimetrically surrounding the latter. This, as a result, will considerably reduce the generating and intensity of any interfacial stresses on the chip-side of the carrier so as to thereby increase the resistance to delamination during potential exposure to moisture, or due to the effects which are encountered as a result of thermal cycling.
Another feature which can be employed pursuant to the invention is the use of through-holes which are formed in the carrier so as to extend between the opposite surface thereof proximate its peripheral edges, beyond or outwardly the dimensional confines of the semiconductor chip, and wherein these through-holes in the substrate or carrier can also be filled by the encapsulating material, thereby further increasing the degree of adhesion thereof to the carrier. The carrier or substrate edges can also be of scalloped configurations in order to enhance the encapsulating and adhesion action by the encapsulating material, and thereby still further strengthening the interconnection or adhesive bonding between the semiconductor chip and the carrier, and resisting any tendency towards delamination between the components of the electronic package.
In view of the foregoing, inventive aspects, it is also possible that the structure of the electronic package in providing this type of a more comprehensive adhesive encapsulation, reduces the likelihood of delamination between the carrier and the mold compound, thereby enabling a material with a higher coefficient thermal expansion to be employed, whereby bending of the composite structure is reduced as the coefficient of thermal expansion (CTE) of the encapsulating material approaches that of the chip carrier or substrate, typically such as 17 ppm/xc2x0 C.
Accordingly, it is an object of the present invention to provide a novel electronic package which is imparted an enhanced degree of interconnection or bonding between a semiconductor chip and a circutized substrate carrier on which the chip is mounted.
Another object of the present invention is to provide a novel encapsulating arrangement interconnecting a semiconductor chip and a circuitized or substrate or carrier on which the chip is mounted so as to increase the degree of adhesion between these components and to thereby reduce the possibility of delamination taking place therebetween.
A further object of the present invention is to provide an electronic package of the type described wherein an encapsulant, such as a thermosetting plastic, encompasses a semiconductor chip which is positioned on a circuitized substrate, and whereby at least portions of a surface of the substrate facing away from the semiconductor chip, and mounting BGA is encompassed by the encapsulating material so as to further enhance the strength of the package against bending and resulting strains causing delamination between the components of the package.
Another object resides in the provision of a method for forming the electronic package comprising the semiconductor chip and the circuitized substrate having the novel encapsulating structure as described herein.